AK7744VT Datasheet, PDF (42/50 Pages) Asahi Kasei Microsystems – 24bit 3ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7744]
7-3-c) External conditional jump code rewrite (during RUN phase)
Two data bytes are used to write an external conditional jump code. Data can be input during both the reset
and operation phases, and input data is set to the specified register at the rising edge of LRCLK. When all data has
been transferred, the RDY terminal goes to "L". Upon completion of writing, it goes to "H". A jump command will be
executed if there is any one agreement between each bit of the 8-bit external condition code and "1"of each bit of the
IFCON field. A write operation from the microcomputer is disabled until RDY goes to "H".
Note: The LRCLK phase is inverted in the I2S-compatible state.
Data transfer procedure
c Command code C4h ( 1 1 0 0 0 1 0 0 )
d Code data
(D7 . . . . . D0)
S_RESET
SCLK
SI
SO
RQ
LRCLK
RDY
11000100 D7 *** D0
max 2LRCLK
L ch R ch
max0.25LRCLK
External condition jump write timing (during RUN phase)
<MS0167-E-00>
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2002/10