AK7744VT Datasheet, PDF (43/50 Pages) Asahi Kasei Microsystems – 24bit 3ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7744]
7-4) Read-out during RUN phase (SO output )
SO outputs data on DBUS (data bus) of the DSP section. Data is set when @MICR the DST field specifies. Setting
of data allows DRDY to go to "H", and data is output synchronized with the falling edge of SCLK. When SI goes to
"H", DRDY goes to "L" to wait for the next command. Once DRDY goes to "H", the data of the last @MICR
command immediately before DRDY goes to "H" will be held until SI goes to "H", and subsequent commands will
be rejected. A maximum of 24 bits are output from SO. After the required number of data (not exceeding 24 bits) is
taken out by SCLK, setting SI to “H” can output the next data.
S_RESET
RQ
SI
@MICR
DRDY
SCLK
SO
Data1
Data2
DM Data1
DLSB
DM Data2 DLSB
SO read (during RUN phase)
(8) ADC section high-pass filter
The AK7744 incorporates a digital high-pass filter (HPF) for canceling DC offset in the ADC. The HPF
cut-off frequency is about 1 Hz (fs = 48 kHz). This cut-off frequency is proportional to the sampling frequency (fs).
Cut-off frequency
48kHz
0.93Hz
44.1kHz
0.86Hz
32kHz
0.62Hz
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2002/10