LU3X34FTR Datasheet, PDF (8/52 Pages) Agere Systems – Quad 3 V 10/100 Ethernet Transceiver TX/FX

LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
Pin Descriptions (continued)
Table 2. Twisted-Pair Magnetic Interface
Pin No.
Pin Name
I/O
6, 11, 28, 33
TX+_[0:3]
O
7, 10, 29, 32
TX–_[0:3]
3, 14, 25, 36
RX–_[0:3]
I
2, 15, 24, 37
RX+_[0:3]
Pin Description
Transmit Driver Pairs. These pins are used to
transmit 100Base-T MLT-3 signals across Category
5 UTP cable. 10Base-T Manchester signals across
Category 3, 4, or 5 UTP cable in twisted-pair opera-
tion or PECL data in fiber mode.
Receive Pair. These pins receive 100Base-T MLT-3
data or 10Base-T Manchester data from the UTP
cable in twisted-pair mode or PECL data in fiber
mode.
Table 3. Twisted-Pair Transceiver Control/Transmitter Control
Pin No.
5, 12, 27, 34
22
127
Pin Name
REF100_[0:3]
REF10
ER
41
TPTXTR
I/O
Pin Description
I
Reference Pin for 100 Mbits/s Twisted-Pair
Driver. The value of the connected resistor is 301 Ω.
I
Reference Pin for 10 Mbits/s Twisted-Pair Driver.
The value for the connected resistor is 4.65 kΩ.
I
Transmit Driver Edge Rate Control. When set to 1,
the rise time of the transmit data will be less than
3.5 ns.
I
Network Interface 3-State Control. When high, the
transmit drivers for the four ports are 3-stated.
Table 4. MII Interface (RMII Mode)
Pin No.
99, 73, 53
113
102
Pin Name*
TXEN_[1:3]
TXEN_0
RMII_RXER_0
112, 111
110, 109
101
RMII_TXD_0[0:1]
RMII_RXD_0[0:1]
CRS_DV_0/SMII_EN
98, 97
96, 95
94
RMII_TXD_1[0:1]
RMII_RXD_1[0:1]
CRS_DV_1/PHYAD[2]
I/O
Pin Description
I
Transmit Enable for Ports 1—3.
I
Transmit Enable for Port 0.
I/O
Receiver Error Output for Port 0. Indicates an
illegal code-group has been received.
I
Transmit Data for Port 0.
I/O
Receive Data for Port 0.
I/O↓ CRS_DV Output for Port 0. During reset, this is an
input pin; logic level of 0 at this pin enables RMII
mode. This pin has an internal 40 kΩ pull-down
resistor that sets the MII interface to RMII mode with-
out an external component. After reset, CRS_DV
output for port 0 is asserted only during receive
activity.
I/O
Transmit Data for Port 1.
O
Receive Data for Port 1.
I/O↓ CRS_DV Output for Port 1. During reset, this is an
input pin for PHY_address[2] configuration. This pin
has an internal 40 kΩ pull-down resistor that sets the
PHY_AD[2] to a 0 without an external component.
After reset, CRS_DV output for port 1 and is
asserted only during receive activity.
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Lucent Technologies Inc.