LU3X34FTR Datasheet, PDF (27/52 Pages) Agere Systems – Quad 3 V 10/100 Ethernet Transceiver TX/FX

Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Functional Description (continued)
Automatic Link Polarity Detection. The
LU3X34FTR's 10Base-T transceiver module incorpo-
rates an automatic link polarity detection circuit. The
inverted polarity is determined when seven consecutive
link pulses of inverted polarity or three consecutive
packets are received with inverted end-of-packet
pulses. If the input polarity is reversed, the error condi-
tion will be automatically corrected and reported in
bit 15 of register 1Ch.
The automatic link polarity detection function can be
disabled by setting bit 3 of register 1Ah.
Clock Synthesizer
The LU3X34FTR implements a clock synthesizer that
generates all the reference clocks needed from a single
external frequency source. The clock source must be a
TTL level signal at 25 MHz ± 50 ppm.
Autonegotiation
The autonegotiation function provides a mechanism for
exchanging configuration information between two
ends of a link segment and automatically selecting the
highest-performance mode of operation supported by
both devices. Fast link pulse (FLP) bursts provide the
signaling used to communicate autonegotiation abilities
between two devices at each end of a link segment. For
further detail regarding autonegotiation, refer to
Clause 28 of the IEEE 802.3u specification. The
LU3X34FTR supports four different Ethernet protocols,
so the inclusion of autonegotiation ensures that the
highest-performance protocol will be selected based on
the ability of the link partner.
The autonegotiation function within the LU3X34FTR
can be controlled either by internal register access or
by the use of configuration pins. At powerup and at
device reset, the configuration pins are sampled. If dis-
abled, autonegotiation will not occur until software
enables bit 12 in register 0. If autonegotiation is
enabled, the negotiation process will commence imme-
diately.
When autonegotiation is enabled, the LU3X34FTR
transmits the abilities programmed into the autonegoti-
ation advertisement register at address 4h via FLP
bursts. Any combination of 10 Mbits/s, 100 Mbits/s,
half-duplex, and full-duplex modes may be selected.
Autonegotiation controls the exchange of configuration
information. Upon successful autonegotiation, the abili-
ties reported by the link partner are stored in the auto-
negotiation link partner ability register at address 5h.
The contents of the autonegotiation link partner ability
register are used to automatically configure to the
highest-performance protocol between the local and
far-end nodes. Software can determine which mode
has been configured by autonegotiation by comparing
the contents of register 04h and 05h and then selecting
the technology whose bit is set in both registers of high-
est priority relative to the following list.
1. 100Base-TX full duplex (highest priority).
2. 100Base-TX half duplex.
3. 10Base-T full duplex.
4. 10Base-T half duplex (lowest priority).
The basic mode control register at address 00h pro-
vides control of enabling, disabling, and restarting of
the autonegotiation function. When autonegotiation is
disabled, the speed selection bit (bit 13) controls
switching between 10 Mbits/s or 100 Mbits/s operation,
while the duplex mode bit (bit 8) controls switching
between full-duplex operation and half-duplex opera-
tion. The speed selection and duplex mode bits have
no effect on the mode of operation when the autonego-
tiation enable bit (bit 12) is set.
The basic mode status register at address 01h indi-
cates the set of available abilities for technology types
(bits 15 to 11), autonegotiation ability (bit 3), and
extended register capability (bit 0). These bits are hard-
wired to indicate the full functionality of the
LU3X34FTR. The BMSR also provides status on:
1. Whether autonegotiation is complete (bit 5).
2. Whether the link partner is advertising that a remote
fault has occurred (bit 4).
3. Whether a valid link has been established (bit 2).
The autonegotiation advertisement register at address
04h indicates the autonegotiation abilities to be adver-
tised by the LU3X34FTR. All available abilities are
transmitted by default, but any ability can be sup-
pressed by writing to this register or configuring exter-
nal pins.
The autonegotiation link partner ability register at
address 05h indicates the abilities of the link partner as
indicated by autonegotiation communication. The con-
tents of this register are considered valid when the
autonegotiation complete bit (bit 5, register address
01h) is set.
Lucent Technologies Inc.
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