LU3X34FTR Datasheet, PDF (39/52 Pages) Agere Systems – Quad 3 V 10/100 Ethernet Transceiver TX/FX

Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers (continued)
Table 24. PHY Control/Status Register (Register 17h) (continued)
Bit(s)
10
9
8
7
6
5
4
3
2
1
0
Name
Description
MF Preamble Suppression
Enable
Speed Status
Duplex Status
Reserved
Reserved
ACTLED Off
1—MDIO preamble suppression enabled
0—MDIO preamble suppression disabled
LU3X34FTR can accept management
frames without preamble as described in
bit 6 of register 1h. This bit allows the user
to enable or disable the preamble sup-
pression function.
1—Part is in 100 Mbit mode
0—Part is in 10 Mbit mode
This value is not defined during the auto-
negotiation period.
1—Part is in full-duplex mode
0—Part is in half-duplex mode
This value is not defined during the auto-
negotiation period.
Reserved.
Reserved.
1—3-state ACTLED output
0—Normal operation
LEDLNK Off
1—3-state LEDLNK output
0—Normal operation
Reserved
Reserved.
LEDFD Off
1—3-state LEDFD output
0—Normal operation
LEDSP Off
1—3-state LEDSP output
0—Normal operation
LED Pulse Stretching Disable 1—LED pulse stretching disabled
0—LED pulse stretching enabled
When set to 1 all LED outputs are
stretched 48 ms—72 ms.
R/W
R/W
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1h
0h
0h
1h
1h
0
0
1h
0
0
0
Table 25. Config 100 Register (Register 18h)
Bit(s)
15
14
13
12
Name
BPSCR
Reserved
Reserved
Reserved
Description
1—Disable scrambler/descrambler
0—Enable scrambler/descrambler
Reserved.
Reserved.
Reserved.
R/W
Default
R/W
FOSEL
RO
0h
RO
0h
RO
0h
Lucent Technologies Inc.
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