LU3X34FTR Datasheet, PDF (35/52 Pages) Agere Systems – Quad 3 V 10/100 Ethernet Transceiver TX/FX

Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers (continued)
Table 18. Advertisement (Register 4h)
Bit(s)
Name
Description
R/W
15
Next Page
1—Capable of next page function
RO
0—Not capable of next page function
This bit is defaults to 0, indicating that
LU3X34FTR is not next page capable.
14
Reserved
Reserved.
RO
13
Remote Fault
1—Remote fault has been detected
R/W
0—No remote fault has been detected
This bit is written by serial management
interface for the purpose of communicat-
ing the remote fault condition to the auto-
negotiation link partner.
12:11
IEEE Reserved
These bits default to 0.
R/W
10
Flow Control
1—MAC sublayer is capable of pause-
R/W
based flow control
0—MAC sublayer not capable of pause-
based flow control
This bit advertises the MAC sublayer has
pause/flow control capability of operation
when set in full-duplex mode. This must
be set only when the PHY is advertising
10FD/100FD modes. At hardware reset,
this bit is set to 1, if the PAUSE pin
detects logic 1.
Note: It is the user’s responsibility to
ensure that the flow control bit is set only
when the PHY is advertising
10FD/100FD modes.
9
Technology Ability Field for This bit defaults to 0, indicating that the
RO
100Base-T4
LU3X34FTR does not support
100Base-T4.
8:5
Technology Ability Field This 4-bit field contains the advertised
R/W
ability of this PHY. At powerup or reset,
the logic level of 100FDEN, 100HDEN,
10FDEN, and 10HDEN pins are latched
into bits 8 through 5, respectively.
4:0
Selector Field
These 5 bits are hardwired to 00001h,
RO
indicating that the LU3X34FTR supports
IEEE 802.3 CSMA/CD.
Default
0h
0h
0h
0h
Pin
0h
Pin
01h
Lucent Technologies Inc.
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