LU3X34FTR Datasheet, PDF (32/52 Pages) Agere Systems – Quad 3 V 10/100 Ethernet Transceiver TX/FX

LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
MII Registers (continued)
Table 14. Control Register (Register 0h) (continued)
Bit(s)
Name
Description
R/W
9
Restart Autonegotiation 1—Restart autonegotiation process
R/W, SC
0—Normal operation
Setting this bit while autonegotiation is
enabled forces a new autonegotiation pro-
cess to start. This bit is self-clearing and
returns to 0 after the autonegotiation pro-
cess has commenced.
8
Duplex Mode
1—Full-duplex mode
R/W
0—Half-duplex mode
If autonegotiation is disabled, this bit
determines the duplex mode for the link.
At powerup or reset, this bit is set to 0 if
the SW_RPTRZ input is low. This bit is set
to 1, if ANEN pin detects a logic 0 and
either FD100 or FD10 pin detects a logic
1.
7
Collision Test (only
1—Enable COL signal test
R/W
applicable while in PHY 0—Disable COL signal test
loopback mode)
When set, this bit will cause the COL sig-
nal of MII interface to be asserted in
response to the assertion of TXEN.
6:0
Reserved
Not used.
RO
Note: While maintaining a good link, modifying any bit in the control register (register 0) will cause the link to drop.
Default
0h
Pin
0h
0h
Table 15. Status Register Bit Definitions (Register 1h)
Bit(s)
Name
Description
R/W
15
100Base-T4
1—Capable of 100Base-T4
RO
0—Not capable of 100Base-T4
This bit is hardwired to 0, indicating that
the LU3X34FTR does not support
100Base-T4.
14
100Base-X Full Duplex 1—Capable of 100Base-X full-duplex
RO
mode
0—Not capable of 100Base-X full-duplex
mode
This bit is hardwired to 1, indicating that
the LU3X34FTR supports 100Base-X
full-duplex mode.
13
100Base-X Half Duplex 1—Capable of 100Base-X half-duplex
RO
mode
0—Not capable of 100Base-X half-duplex
mode
This bit is hardwired to 1, indicating that
the LU3X34FTR supports 100Base-X
half-duplex mode.
Default
0h
1h
1h
32
Lucent Technologies Inc.