LU3X34FTR Datasheet, PDF (40/52 Pages) Agere Systems – Quad 3 V 10/100 Ethernet Transceiver TX/FX

LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
MII Registers (continued)
Table 25. Config 100 Register (Register 18h) (continued)
Bit(s)
11
10
9
8:6
5
4
3
2:0
Name
Enable FEFI
Reserved
Force Good Link 100
Reserved
Accept Halt
Load Seed
Burst Mode
Reserved
Description
R/W
1—Enable FEFI
R/W
0—Disable FEFI
This bit enables/disables far-end fault indi-
cator function for 100Base-FX and
10Base-T operation. It is initialized to the
logic level of FOSEL pin (pin 124, 117, 52,
and 46) at powerup or reset. After reset,
this bit is writable if and only if the FOSEL
register (bit 14 of register 17h) is set.
Reserved.
RO
1—Force good link in 100 Mbit mode
R/W
0—Normal operation
Reserved.
RO
1—Passes halt symbols to the MII
R/W
0—Normal operation
1—Loads the scrambler seed
0—Normal operation
Setting this bit loads the user seed stored
in register 19h into the 100Base-X scram-
bler. The content of this bit returns to 0
after the loading process is completed and
no transmit is active.
R/W, SC
1—Burst mode
R/W
0—Normal operation
Setting this bit expands the 722 µs scram-
bler time-out period to 2,000 µs.
Reserved.
RO
Default
Pin
0h
0h
1h
0h
0h
0h
0h
Table 26. PHY Address Register (Register 19h)
Bit(s)
15:11
10:5
4:0
Name
Reserved
User Seed
PHY Address
Description
R/W Default
Reserved.
RO
0h
User-modifiable seed data. When the
R/W
21h
load seed bit (bit 4 of register 18h) is set,
bits 10 through 0 of this register are
loaded into the 100Base-X scrambler.
These 5 bits store the part address used R/W
Pin
by the serial management interface. Top
three of these bits are latched from the
pins during powerup of hard reset. Lower
2 bits are assigned automatically.
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