LU3X34FTR Datasheet, PDF (28/52 Pages) Agere Systems – Quad 3 V 10/100 Ethernet Transceiver TX/FX

LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
Functional Description (continued)
Reset Operation
The LU3X34FTR can be reset either by hardware or
software. A hardware reset is accomplished by apply-
ing a negative pulse, with a duration of at least 1 ms to
the RSTZ pin of the LU3X34FTR during normal opera-
tion. A software reset is activated by setting the reset
bit in the basic mode control register (bit 15, register
00h). This bit is self-clearing and, when set, will return
a value of 1 until the software reset operation has com-
pleted.
Hardware reset operation samples the pins and initial-
izes all registers to their default values. This process
includes re-evaluation of all hardware-configurable reg-
isters. A hardware reset affects all four PHYs in the
device.
A software reset can reset an individual PHY, and it
does not latch the external pins or reset the registers to
their respective default values.
Logic levels on several I/O pins are detected during a
hardware reset to determine the initial functionality of
LU3X34FTR. Some of these pins are used as output
ports after reset operation.
Care must be taken to ensure that the configuration
setup will not interfere with normal operation. Dedi-
cated configuration pins can be tied to Vcc or ground
directly. Configuration pins multiplexed with logic level
output functions should be either weakly pulled up or
weakly pulled down through resistors. Configuration
pins multiplexed with LED outputs should be set up
with one of the following circuits shown in Figure 11.
The 10 kΩ resistor is required only for nondefault con-
figuartion.
Pins ANEN, FD10, FD100, and HD100 have internal
pull-up resistors, making their default value a 1 without
any external components. Pins FOSEL, SMII_EN, and
PHYAD[2:4] have internal pull-down resistors, making
their default value a 0 without any external compo-
nents.
Note: The MDIO pin is pulled low during reset.
I/O PIN
10 kΩ
I/O PIN
10 kΩ
LOGIC 1 CONFIGURATION
LOGIC 0 CONFIGURATION
Figure 11. LED Configuration
5-6783(F).a
PHY Address
The PHY device address is stored in bits [4:0] of the PHY address register (register address 19h). The upper 3 bits
of this field are initialized by the three I/O pins designated as PHY[4:2] during powerup or hardware reset and can
be changed afterward by writing into this register address (19h). The lower 2 bits are initialized to 00 and represent
the PHY address for port 0. The PHY address for all subsequent ports are increments from this base address (i.e.,
PHY address for port 0 = 10h, PHY address for port 1 = 11h, PHY address for port 2 = 12h, PHY address for
port 3 = 13h). These unique 5-bit addresses are used during serial management interface communication.
28
Lucent Technologies Inc.