LU3X34FTR Datasheet, PDF (34/52 Pages) Agere Systems – Quad 3 V 10/100 Ethernet Transceiver TX/FX

LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
MII Registers (continued)
Table 15. Status Register Bit Definitions (Register 1h) (continued)
Bit(s)
3
2
1
0
Name
Description
R/W
Autonegotiation Ability 1—Capable of autonegotiation
RO
0—Not capable of autonegotiation
This bit defaults to 1, indicating that
LU3X34FTR is capable of autonegotia-
tion.
Link Status
1—Link is up
RO,
0—Link is down
LL
This bit reflects the current state of the
link-test-fail state machine. Loss of a valid
link causes a 0 latched into this bit. It
remains 0 until this register is read by the
serial management interface.
Jabber Detect
1—Jabber condition detected
RO,
0—Jabber condition not detected
LH
During 10Base-T operation, this bit indi-
cates the occurrence of a jabber condi-
tion. It is implemented with a latching
function so that it becomes set until it is
cleared by a read.
Extended Capability 1—Extended register set
RO
0—No extended register set
This bit defaults to 1, indicating that the
LU3X34FTR implements extended regis-
ters.
Default
1h
0h
0h
1h
Table 16. PHY Identifier (Register 2h)
Bit(s)
15:0
Name
PHY-ID[15:0]
Description R/W
IEEE address
RO
Default
0043h
Table 17. PHY Identifier (Register 3h)
Bit(s)
15:0
Name
PHY-ID[15:0]
Description R/W
IEEE
RO
address/Model
No./ Rev. No.
Default
7440h
34
Lucent Technologies Inc.