LU3X34FTR Datasheet, PDF (30/52 Pages) Agere Systems – Quad 3 V 10/100 Ethernet Transceiver TX/FX

LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
MII Registers
Table 13. MII Management Registers
Address
0h
1h
2h—3h
4h
5h
6h
7h—Fh
12h
13h
15h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
Register Name
Control Register
Status Register
PHY Identifier Register
Autonegotiation Advertisement Register
Autonegotiation Link Partner Ability Register
Autonegotiation Expansion Register
IEEE Reserved
Isolate Counter
False Carrier Counter
Receive Error Counter
PHY Control/Status Register
Config 100 Register
PHY Address Register
Config 10 Register
Status 100 Register
Status 10 Register
Interrupt Mask Register
Interrupt Status Register
Basic/Extended
B
B
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
Legend:
RO Read only.
R/W Read and write capable.
SC Self-clearing.
LL Latching low, unlatch on read.
LH Latching high, unlatch on read.
COR Clear on read.
Table 14. Control Register (Register 0h)
Bit(s)
15
Name
Reset
Description
R/W
1—PHY reset
R/W
0—Normal operation
SC
Setting this bit initiates the software reset
function that resets the selected port,
except for the phase-locked loop circuit. It
will not relatch in all hardware configura-
tion pin values, but it will set all registers to
their default values. The software reset
process takes 25 µs to complete. This bit,
which is self-clearing, returns a value of 1
until the reset process is complete.
Default
0h
30
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