LU3X34FTR Datasheet, PDF (2/52 Pages) Agere Systems – Quad 3 V 10/100 Ethernet Transceiver TX/FX

LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
Table of Contents
Contents
Page
Overview................................................................................................................................................................... 1
Features ................................................................................................................................................................... 1
Description................................................................................................................................................................ 4
Pin Information ......................................................................................................................................................... 5
Pin Descriptions........................................................................................................................................................ 7
Functional Description ............................................................................................................................................ 13
Reduced Media Independent Interface (RMII) .................................................................................................... 13
Serial Media Independent Interface (SMII).......................................................................................................... 15
Media Independent Interface (MII)—Internal....................................................................................................... 17
100Base-X Module.............................................................................................................................................. 19
Scrambler Block .................................................................................................................................................. 22
100Base-TX Transceiver..................................................................................................................................... 24
10Base-T Module ................................................................................................................................................ 25
Reset Operation .................................................................................................................................................. 28
MII Registers .......................................................................................................................................................... 30
dc and ac Specifications......................................................................................................................................... 43
Absolute Maximum Ratings................................................................................................................................. 43
Clock Timing........................................................................................................................................................... 44
Outline Diagram...................................................................................................................................................... 50
128-Pin SQFP ..................................................................................................................................................... 50
Ordering Information............................................................................................................................................... 51
Tables
Page
Table 1. MII Interface Cross-Reference ................................................................................................................... 7
Table 2. Twisted-Pair Magnetic Interface ................................................................................................................. 8
Table 3. Twisted-Pair Transceiver Control/Transmitter Control ................................................................................. 8
Table 4. MII Interface (RMII Mode) .......................................................................................................................... 8
Table 5. MII Interface (SMII Mode) .......................................................................................................................... 9
Table 6. LED/Configuration Pins............................................................................................................................ 10
Table 7. Special Mode Configurations ................................................................................................................... 11
Table 8. Clock and Chip Reset .............................................................................................................................. 12
Table 9. Power and Ground ................................................................................................................................... 12
Table 10. Receive Data/Status Encoding .............................................................................................................. 16
Table 11. Symbol Code Scrambler ........................................................................................................................ 21
Table 12. Autonegotiation ...................................................................................................................................... 29
Table 13. MII Management Registers .................................................................................................................... 30
Table 14. Control Register (Register 0h) ............................................................................................................... 30
Table 15. Status Register Bit Definitions (Register 1h).......................................................................................... 32
Table 16. PHY Identifier (Register 2h) ................................................................................................................... 34
Table 17. PHY Identifier (Register 3h) ................................................................................................................... 34
Table 18. Advertisement (Register 4h) .................................................................................................................. 35
Table 19. Autonegotiation Link Partner Ability (Register 5h) ................................................................................. 36
Table 20. Autonegotiation Expansion Register (Register 6h) ................................................................................ 36
Table 21. Programable LED (Register 11h) ........................................................................................................... 37
Table 22. False Carrier Counter (Register 13h) ..................................................................................................... 38
Table 23. Receive Error Counter (Register 15h).................................................................................................... 38
Table 24. PHY Control/Status Register (Register 17h).......................................................................................... 38
Table 25. Config 100 Register (Register 18h)........................................................................................................ 39
Table 26. PHY Address Register (Register 19h) ................................................................................................... 40
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