LU3X34FTR Datasheet, PDF (33/52 Pages) Agere Systems – Quad 3 V 10/100 Ethernet Transceiver TX/FX

Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers (continued)
Table 15. Status Register Bit Definitions (Register 1h) (continued)
Bit(s)
12
11
10
9:7
6
5
4
Name
Description
10 Mbits/s Full Duplex
1—Capable of 10 Mbits/s full-duplex
mode
0—Not capable of 10 Mbits/s full-duplex
mode
This bit is hardwired to 1, indicating that
the LU3X34FTR supports 10Base-T
full-duplex mode.
10 Mbits/s Half Duplex
1—Capable of 10 Mbits/s half-duplex
mode
0—Not capable of 10 Mbits/s half-duplex
mode
This bit is hardwired to 1, indicating that
the LU3X34FTR supports 10Base-T
half-duplex mode.
100Base-T2
1—Capable of 100Base-T2
0—Not capable of 100Base-T2
This bit is hardwired to 0, indicating that
the LU3X34FTR does not support
100Base-T2.
Reserved
Ignore when read.
MF Preamble Suppression 1—Accepts management frames with
preamble suppressed
0—Will not accept management frames
with preamble suppressed
This bit is hardwired to 1, indicating that
the LU3X34FTR accepts management
frame without preamble. A minimum of 32
preamble bits are required following
power-on or hardware reset. One idle bit
is required between any two manage-
ment transactions as per IEEE 802.3u
specification.
Autonegotiation Complete
Remote Fault
1—Autonegotiation process completed
0—Autonegotiation process not com-
pleted
If autonegotiation is enabled, this bit indi-
cates whether the autonegotiation pro-
cess has been completed.
1—Remote fault detected
0—Remote fault not detected
This bit is latched to 1 if the RF bit in the
autonegotiation link partner ability regis-
ter (bit 13, register address 05h) is set or
the receive channel meets the far-end
fault indication function criteria. It is
unlatched when this register is read.
R/W
RO
RO
RO
RO
RO
RO
RO, LH
Default
1h
1h
0h
0h
1h
0h
0h
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