Z86L972 Datasheet, PDF (66/91 Pages) Zilog, Inc. – Low-Voltage Microcontrollers

Z86L972/Z86L973/Z86L974
Low-Voltage Microcontrollers
59
Whenever a power-on reset is executed, the IRQ is reset to 00h and disabled.
Before the IRQ accepts requests, it must be enabled by executing an enable inter-
rupts instruction.
Note: IRQ is always cleared to 00h and is in read-only mode until the
first EI instruction that enables the IRQ to be read/write. Setting
the Global Interrupt Enable bit in the Interrupt Mask Register
(IMR bit 7) does not enable the IRQ. Execution of an EI
instruction is required.
For polled processing, IRQ must be initialized by an EI instruction. To properly ini-
tialize the IRQ, the following code is provided:
CLR IMR ; make sure vectored interrupts are disabled
EI
; enable IRQ, otherwise it is read only
; not necessary, if interrupts were previously
; enabled
DI
; disable interrupt handling
IMR is cleared before the IRQ enabling sequence to ensure no unexpected inter-
rupts occur when EI is executed. This code sequence must be executed before
programming the application required values for IPR and IMR.
I/O Port Control Registers
Each of the four ports (Ports 2, 4, 5, and 6) has an input register, an output regis-
ter, and an associated buffer and control logic. Because there are separate input
and output registers associated with each port, writing bits defined as inputs
stores the data in the output register. This data cannot be read as long as the bits
are defined as inputs. However, if the bits are reconfigured as output, the data
stored in the output register is reflected on the output pins and can then be read.
This mechanism allows you to initialize the outputs before driving their loads.
Port Configuration Registers (P456CON and P3M)
The port configuration register (described in Table 22) switches the comparator
inputs from digital to analog and allows Ports 4, 5, and/or 6 to be switched from
push/pull active outputs to open drain outputs. In ZiLOG Test Mode, bit 3 of this
register is used to enable the Address Strobe/Data Strobe. Bit 3 is not available in
User Mode.
PS010504-1002
PRELIMINARY