Z86L972 Datasheet, PDF (28/91 Pages) Zilog, Inc. – Low-Voltage Microcontrollers

Z86L972/Z86L973/Z86L974
Low-Voltage Microcontrollers
21
selected, the WDT is initially enabled by executing the WDT instruction and
refreshed on subsequent executions of the WDT instruction.
The WDT instruction does not affect the Zero (Z), Sign (S), and Overflow (V) flags.
Permanently enabled WDTs are always enabled, and the WDT instruction is used
to refresh it. The WDT cannot be disabled after it has been initially enabled. The
WDT is off during both HALT and STOP modes.
The WDT circuit is driven by an on-board RC oscillator. The time-out period for the
WDT is fixed to a typical value (see Table 53 on page 81).
Power Management
In addition to the standard RUN mode, the Z8 supports three power-down modes
to minimize device current consumption. The following three modes are sup-
ported:
• HALT
• STOP
• Low-Voltage Standby
Table 6 shows the status of the internal CPU clock (SCLK), the internal Timer
clock (TCLK), the external oscillator, and the Watch-Dog Timer during the RUN
mode and three low-power modes.
Table 6. Clock Status in Operating Modes
Operating Mode
SCLK TCLK External OSC WDT*
RUN
On On On
On
HALT
Off On On
Off
STOP
Off Off Off
Off
Low-Voltage Standby Off Off Off
Off
Note: * When WDT is enabled by the mask option bit
Using the Power-Down Modes
In order to enter HALT or STOP mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction. You can flush the
instruction pipeline by executing a NOP (Op Code = FFh) immediately before the
appropriate sleep instruction. For example:
Mnemonic Comment
Op Code
NOP
; clear the pipeline FFh
STOP
; enter STOP mode 6Fh
PS010504-1002
PRELIMINARY