Z86L972 Datasheet, PDF (15/91 Pages) Zilog, Inc. – Low-Voltage Microcontrollers

Z86L972/Z86L973/Z86L974
Low-Voltage Microcontrollers
8
Table 2. Pin Descriptions (Continued)
Symbol
XTAL2
V_DD
V_{DD_padring}
V_SS
Pin #
40 48
PDIP SSOP Direction Description
15 17
Output Crystal, Oscillator clock
12, 13 13, 14,
15
Z8 core power supply
14 16
Power supply (pad ring)
6, 7, 7, 8,
32 37, 38
Ground
Operational Description
Central Processing Unit (CPU) Description
The Z8 architecture is characterized by a flexible I/O scheme, an efficient register
and address space structure and a number of ancillary features for cost-sensitive,
high-volume embedded control applications. ROM-based products are geared for
high-volume production (where the software is stable) and one-time programma-
ble equivalents for prototyping as well as volume production where time to market
or code flexibility is critical.
Architecture Type
The Z8 register-oriented architecture centers around an internal register file com-
posed of 256 consecutive bytes, known as the standard register file. The standard
register file consists of 4 I/O port registers (R2, R4, R5, and R6), 12 control and
status registers, 233 general-purpose registers, and 7 registers reserved for future
expansion. In addition to the standard register file, the Z86L972/Z86L973/
Z86L974 family uses 21 control and status registers located in the Z8 expanded
register file. Any general-purpose register can be used as an accumulator and
address pointer or an index, data, or stack register.
All active registers can be referenced or modified by any instruction that accesses
an 8-bit register, without the requirement for special instructions. Registers
accessed as 16 bits are treated as even-odd register pairs. In this case, the data’s
most significant byte (MSB) is stored in the even-numbered register, while the
least significant byte (LSB) goes into the next higher odd-numbered register.
The Z8 CPU has an instruction set designed for the large register file. The instruc-
tion set provides a full compliment of 8-bit arithmetic and logical operations. BCD
operations are supported using a decimal adjustment of binary values, and 16-bit
quantities for addresses and counters can be incremented and decremented. Bit
manipulation and Rotate and Shift instructions complete the data-manipulation
PS010504-1002
PRELIMINARY