Z86L972 Datasheet, PDF(42/91 Page) Zilog, Inc. – Low-Voltage Microcontrollers

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Z86L972 Datasheet, PDF (42/91 Pages) Zilog, Inc. – Low-Voltage Microcontrollers

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Z86L972/Z86L973/Z86L974

Low-Voltage Microcontrollers

The time interval (i) until end-of-count, is given by

i=txpxv

where t is 8 divided by XTAL frequency, p is the prescaler value (1 â 64), and v is

the counter/timer value (1 â 256). The prescaler and counter/timer are true divide-

by-n counters.

TOUT Modes

The Timer Mode register TMR (F1h) (Figure 22) is used in conjunction with the

Port 5 Mode register P5M to configure P56 for TOUT operation. In order for TOUT to

function, P56 must be defined as an output line by setting P5M bit D6 to 0. Output

is controlled by one of the counter/timers (T0 or T1) or the internal clock.

R241 TMR

Timer Mode Register

(F1h; Read/Write)

D7 D6

0 = No function

1 = Load T1

TOUT modes

TOUT off = 00

Reserved = 01

T1 out = 10

Internal clock out = 11

Figure 22. Timer Mode Register TOUT Operation

The P56 output is selected by TMR bits D7 and D6. T1 is selected by setting D7

and D6 to 1 and 0, respectively. The counter/timer TOUT mode is turned off by set-

ting TMR bits D7 and D6 both to 0, freeing P36 to be a data output line.

TOUT is initialized to a logic 1 whenever the TMR Load bit D2 is set to 1.

At end-of-count, the interrupt request line IRQ5 clocks a toggle flip-flop. The out-

put of this flip-flop drives the TOUT line P56. In all cases, when the counter/timer

reaches its end-of-count, TOUT toggles to its opposite state (see Figure 23). If, for

example, the counter/timer is in continuous counting mode, TOUT has a 50% duty

cycle output. You can control the duty cycle by varying the initial values after each

end-of-count.

PS010504-1002

PRELIMINARY

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