Z86L972 Datasheet, PDF (37/91 Pages) Zilog, Inc. – Low-Voltage Microcontrollers

Z86L972/Z86L973/Z86L974
Low-Voltage Microcontrollers
30
Counter/timer 1 is driven by a timer clock generated by dividing the internal clock
by four. The divide-by-four stage, the 6-bit prescaler, and the 8-bit counter/timer
form a synchronous 16-bit divide chain. Counter/timer T₁ can also be driven by an
external input (T_IN) using Port P52. Port P5₆ can serve as a timer output (T_OUT)
through which T₁ or the internal clock can be output. The timer output toggles at
the end-of-count. Figure 15 is a block diagram of the counter/timer.
OSC
+2
Internal
Clock
External Clock
Clock
Logic
+4
+2
T_OUT
P5₆
6-Bit
Down Counter
8-Bit
Down Counter
IRQ5
Internal Clock
Gated Clock
Triggered Clock
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
T_INP3₁
Write
Write
Read
Internal Data Bus
Figure 15. T₁ Counter/Timer Block Diagram
PS010504-1002
PRELIMINARY