Z86L972 Datasheet, PDF (64/91 Pages) Zilog, Inc. – Low-Voltage Microcontrollers

Z86L972/Z86L973/Z86L974
Low-Voltage Microcontrollers
57
Interrupt Priority Register (IPR)
The IPR, as described in Table 20, is a write-only register that sets priorities for
the vectored interrupts in order to resolve simultaneous interrupt requests. There
are 48 sequence possibilities for interrupts. The six interrupts, IRQ₀ to IRQ₅, are
divided into three groups of two interrupt requests each, as follows:
• Group A consists of IRQ₃ and IRQ₅
• Group B consists of IRQ₀ and IRQ₂
• Group C consists of IRQ₁ and IRQ₄
)
Table 20. IPR (Group/Bank 0Fh, Register 9)
Bit
7
6
5
4
3
2
1
0
Bit/Field Reserved
Grp A
IRQ3_5 Int_Group
Grp B Grp C Int_
IRQ0_2 IRQ1_4 Group
R/W
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W Value Description
76______ Reserved
W
X
No Effect
__5_____ Grp A Priority: W
IRQ₃ and IRQ₅
___43__0 Interrupt Group W
Priority
1
IRQ₃>IRQ₅ (Group A)
0
IRQ₅>IRQ₃
111
Reserved
110
B>A>C
101 C>B>A
100 B>C>A
011
A>C>B
010 A>B>C
001 C>A>B
000 Reserved
_____2__ Grp B Priority: W
1
IRQ₀ and IRQ₂
0
______1_ Grp C Priority: W
1
IRQ₁ and IRQ₄
0
IRQ₀>IRQ₂ (Group B)
IRQ₂>IRQ₀
IRQ₄>IRQ₁ (Group C)
IRQ₁>IRQ₄
Priorities can be set both within and between groups using the IPR. Bits 1, 2, and
5 of the IPR define the priority of individual members within the groups. Bits 0, 3,
and 4 are encoded to define six priority orders between the three groups. Bits 6
and 7 are reserved.
PS010504-1002
PRELIMINARY