Z86L972 Datasheet, PDF (45/91 Pages) Zilog, Inc. – Low-Voltage Microcontrollers

Z86L972/Z86L973/Z86L974
Low-Voltage Microcontrollers
38
Each High-to-Low transition on T_IN generates interrupt request IRQ₀, regardless
of the selected T_IN mode or the enabled/disabled state of T₁. IRQ₀ must therefore
be masked or enabled according to the needs of the application.
External Clock Input Mode
The T_IN External Clock Input mode (TMR bits D₅ and D₄ both set to 0) supports
the counting of external events, where an event is considered to be a High-to-Low
transition on T_IN (see Figure 27) occurrence (single-pass mode) or on every nth
occurrence (continuous mode) of that event.
TMR
D₅–D₄ = 00
T_IN clock
P5₂
D
D
PRE1 T1
IRQ5
Internal clock
Figure 27. External Clock Input Mode
IRQ0
Gated Internal Clock Mode
The T_IN Gated Internal Clock mode (TMR bits D₅ and D₄ set to 0 and 1, respec-
tively) measures the duration of an external event. In this mode, the T₁ prescaler
is driven by the internal timer clock, gated by a High level on T_IN (see Figure 28).
T₁ counts while T_IN is High and stops counting when T_IN is Low. Interrupt request
IRQ₀ is generated on the High-to-Low transition of T_IN, signaling the end of the
gate input. Interrupt request IRQ₅ is generated if T₁ reaches its end-of-count.
OSC
+2
Internal clock
TMR
D₅–D₄ = 01
+4
PRE1 T1
IRQ5
T_IN
gate
P5₂
D
D
IRQ0
Figure 28. Gated Clock Input Mode
PS010504-1002
PRELIMINARY