Z86L972 Datasheet, PDF (27/91 Pages) Zilog, Inc. – Low-Voltage Microcontrollers

Z86L972/Z86L973/Z86L974
Low-Voltage Microcontrollers
20
Table 5. Control and Status Register Reset Conditions (Continued)
Register Function
Port 5 SMR Source
Notes:
Address
Reset Value
Grp/Bnk Register Symbol R/W 7 6 5 4 3 2 1 0
0Fh r5
P5SMR
R/W 0 0 0 0 0 0 0 0
†_{This register is not reset following Stop Mode Recovery (SMR).}
*This bit is not reset following SMR.
X means this bit is undefined at POR and is not reset following SMR.
**In OTP, the default for P43 is open-drain output at power up; you need to
initialize the P43 data. In the mask part, the P43 output is disabled until it is
configured as output.
Power-On Reset
A POR (cold start) always resets the Z8 control and status registers to their default
conditions. A POR sets bit 7 of the Stop Mode Recovery register to 0 to indicate
that a cold start has occurred.
A timer circuit clocked by a dedicated on-board RC oscillator is used for the
Power-On Reset Timer (TPOR) function. The POR time is specified as T_POR.
T_POR time allows V_CC and the oscillator circuit to stabilize before instruction exe-
cution begins.
The POR delay timer circuit is a one-shot timer triggered by one of three condi-
tions:
• Power Fail to Power OK status including recovery from Low Voltage (V_LV)
Standby mode
• STOP-Mode Recovery (when bit 5 of the SMR register = 1)
• WDT time-out
Under normal operating conditions, a stop mode recovery event always triggers
the POR delay timer. This delay is necessary to allow the external oscillator time
to stabilize. When using an RC or LC oscillator (with a low Q factor), the shorter
wake-up time means the delay can be eliminated.
Bit 5 of the SMR register selects whether the POR timer delay is used after Stop-
Mode Recovery or is bypassed. If bit 5 =1, then the POR timer delay is used. If bit
5 = 0, then the POR timer delay is bypassed. In this case, the SMR source must
be held in the recovery state for 5 TpC to pass the Reset signal internally.
Watch-Dog Timer (WDT)
The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its
terminal count. When operating in the RUN modes, a WDT reset is functionally
equivalent to a hardware POR reset. If the mask option of the permanently
enabled watch-dog timer is selected, it runs when power up. If the option is not
PS010504-1002
PRELIMINARY