Z86L972 Datasheet, PDF (25/91 Pages) Zilog, Inc. – Low-Voltage Microcontrollers

Z86L972/Z86L973/Z86L974
Low-Voltage Microcontrollers
18
start the interrupt process. However, the IPR does not have to be initialized for
polled processing.
Interrupts must be globally enabled using the EI instruction. Setting bit 7 of the
IMR is not sufficient. Subsequent to this EI instruction, interrupts can be enabled
either by IMR manipulation or by use of the EI instruction, with equivalent effects.
Additionally, interrupts must be disabled by executing a DI instruction before the
IPRs or IMRs can be modified. Interrupts can then be enabled by executing an EI
instruction.
IRQ Software Interrupt Generation
IRQ can be used to generate software interrupts by specifying IRQ as the destina-
tion of any instruction referencing the Z8 Standard Register File. These Software
Interrupts (SWIs) are controlled in the same manner as hardware-generated
requests (in other words, the IPR and the IMR control the priority and enabling of
each SWI level).
To generate a SWI, the request bit in the IRQ is set as follows:
OR IRQ, #NUMBER
where the immediate data, NUMBER, has a 1 in the bit position corresponding to
the appropriate level of the SWI.
For example, for an SWI on IRQ5, NUMBER would have a 1 in bit 5. With this
instruction, if the interrupt system is globally enabled, IRQ5 is enabled, and there
are no higher priority pending requests, control is transferred to the service routine
pointed to by the IRQ5 vector.
Reset Conditions
A system reset overrides all other operating conditions and puts the Z8 into a
known state. The control and status registers are reset to their default conditions
after a power-on reset (POR) or a Watch-Dog Timer (WDT) time-out while in RUN
mode. The control and status registers are not reset to their default conditions
after Stop Mode Recovery (SMR) while in HALT or STOP mode.
General-purpose registers are undefined after the device is powered up. Reset-
ting the Z8 does not affect the contents of the general-purpose registers. The reg-
isters keep their most recent value after any reset, as long as the reset occurs in
the specified V_CC operating range. Registers do not keep their most recent state
from a V_LV reset, if V_CC drops below V_RAM (see Table 51 on page 78).
Following a reset (see Table 5), the first routine executed must be one that initial-
izes the control registers to the required system configuration.
PS010504-1002
PRELIMINARY