Z86L972 Datasheet, PDF (24/91 Pages) Zilog, Inc. – Low-Voltage Microcontrollers

Z86L972/Z86L973/Z86L974
Low-Voltage Microcontrollers
17
Figure 9. IRQ Logic
Internal interrupt requests are sampled during the most recent clock cycle before
an Op Code fetch (see Figure 10.) External interrupt requests are sampled two
internal clocks earlier than internal interrupt requests because of the synchroniz-
ing flip-flops shown in Figure 8.
Figure 10. Interrupt Request Timing
At sample time, the interrupt request is transferred to the second flip-flop shown in
Figure 9, which drives the interrupt mask and priority logic. When an interrupt
cycle occurs, this flip-flop is reset only for the highest priority level that is enabled.
You have direct access to the second flip-flop by reading and writing to the IRQ.
The IRQ is read by specifying it as the source register of an instruction, and the
IRQ is written by specifying it as the destination register.
Interrupt Initialization
After RESET, all interrupts are disabled and must be re-initialized before vectored
or polled interrupt processing can begin. The Interrupt Priority Register, Interrupt
Mask Register, and Interrupt Request Register must be initialized, in that order, to
PS010504-1002
PRELIMINARY