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| Z86L972 Datasheet, PDF (63/91 Pages) Zilog, Inc. – Low-Voltage Microcontrollers | |||
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Z86L972/Z86L973/Z86L974
Low-Voltage Microcontrollers
56
Interrupt Mask Register
The IMR, as described in Table 19, individually or globally enables the six interrupt
requests. Bit 7 of the IMR is the master enable and must be set before any of the
individual interrupt requests can be recognized. Bit 7 must be set and reset by the
enable interrupts and disable interrupts instructions only. The IMR is automatically
reset during an interrupt service routine and set following the execution of an
Interrupt Return (IRET) instruction.
Table 19. IMR (Group/Bank 0Fh, Register B)
Bit
7
6
5
Bit/Field
Re-
Master served IRQ5
R/W
R/W R/W R/W
Reset
0
0
0
R = Read, W = Write, X = Indeterminate
Bit
Position Bit/Field
R/W
7_______ Master
R/W
_6______ Reserved
__5_____ IRQ5
___4____ IRQ4
____3___ IRQ3
_____2__ IRQ2
______1_ IRQ1
_______0 IRQ0
R
W
R/W
R/W
R/W
R/W
R/W
R/W
4
IRQ4
R/W
0
Value
1
0
1
X
1
0
1
0
1
0
1
0
1
0
1
0
3
2
1
IRQ3
R/W
0
IRQ2
R/W
0
IRQ1
R/W
0
Description
Enable Master Interrupt
Disable Master Interrupt
Always reads 1
No Effect
Enable IRQ5
Disable IRQ5
Enable IRQ4
Disable IRQ4
Enable IRQ3
Disable IRQ3
Enable IRQ2
Disable IRQ2
Enable IRQ1
Disable IRQ1
Enable IRQ0
Disable IRQ0
Note: Bit 7 must be reset by the DI instruction before the contents of
the Interrupt Mask Register or the Interrupt Priority Register are
changed except in the following situations:
0
IRQ0
R/W
0
â Immediately after a hardware reset
â Immediately after executing an interrupt service routine and before IMR bit
7 has been set by any instruction
PS010504-1002
PRELIMINARY
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