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XAPP454 Datasheet, PDF (9/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs
DDR2 SDRAM Controller Modules
R
Table 1: Read Data Timing (Cont’d)
Parameter
Value
(ps)
TQHS
400
TDS
–70
TDH
130
TPACKAGE_SKEW
TLOCAL_CLOCK_SKEW
TPCB_LAYOUT_SKEW
Total Uncertainties
Data Valid Window
Boundaries
Data Valid Window
60
65
50
1492
Leading Edge
Uncertainties
(ps)
–70
0
60
65
50
405
405
Trailing Edge
Uncertainties
(ps)
400
0
130
60
65
50
705
1897
Meaning
Hold skew factor for DQ from Micron
MT47H16M16BG-37E DDR2 SDRAM
Data Sheet.
Setup time for RAM16X1D from Spartan-3A
FPGA Family: Data Sheet [Ref 2] for -5 speed
grade.
Hold time of FIFO. This value is taken from
Spartan-3A FPGA Family: Data Sheet [Ref 2]
for -5 speed grade.
Worst-case package skew.
Worst-case local clock line skew.
Skew between data and strobes on the board.
Total uncertainties for leading edge and
trailing edge uncertainties.
Data valid window is TDATA_PERIOD –
(Leading edge uncertainties +
Trailing edge uncertainties).
LUT Selected Banks
Table 2 shows the LUT selection table when left and right banks are used for data and strobe
pins in an XC3S700A-5FG484 device. At normal temperature, two multiplexers of the delay
circuit are selected by the calibration circuit to delay the strobe.
The number of multiplexers in the DQS path depends only on the number of LUTs in a clock
phase. This mapping is constant across frequencies up to 166 MHz. Thus, the entire design is
frequency-independent.
Table 2: LUT Selection for Left and Right Implementations
Parameter (ps)
DQ Data Delay
Local Clock Route Delay
DQS Delay IOB to LUT
LUT Delay
Number of LUTs in a Clock Phase
Number of LUTS to Delay DQS
Total DQS Delay
Total Extra DQS Delay
Data Valid Window (Lower Bound)
Nominal
384
397
450
620
5
2
1467
1083
405
90%
3456
357
405
558
5
2
1320
1424.7
400
80%
307
286
324
496
6
3
1670
1362
394
70%
269
200
227
434
7
4
1376.9
1192
389
60%
230
120
136
372
8
3
1624
1394
383
50%
192
60
68
310
10
4
1354
1162
378
40%
154
24
27
248
13
4
1083
929
372
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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