XAPP454 Datasheet, PDF (12/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

DDR2 SDRAM Controller Modules
R
Table 4: Address and Command Data Timing (Cont’d)
Parameter
Value (ps)
Leading edge
uncertainties
T_{PCB_LAYOUT_SKEW}
50
50
T_{CLKOUT_PHASE}
210
210
Total Uncertainties
870
Margin
4284
Trailing edge
uncertainties
50
210
870
Meaning
Skew between address and control signals
on the board.
Phase offset between DCM outputs from
Spartan-3A FPGA data sheet [Ref 2].
• Leading edge uncertainties is the
sum of the T_IS, T_{PACKAGE_SKEW},
T_JITTER, T_{CLOCK_TREE_SKEW},
T_{PCB_LAYOUT_SKEW}, and
T_{CLKOUT_PHASE.}
• Trailing edge uncertainties is the sum
of the T_IH, T_{PACKAGE_SKEW}, T_JITTER,
T_{CLOCK_TREE_SKEW},
T_{PCB_LAYOUT_SKEW}, and
T_{CLKOUT_PHASE.}
Margin is equal to T_CLOCK –
(Leading edge uncertainties +
Trailing edge uncertainties).
The loopback timing data shown in Table 5 is related to FIFO write enable generation for the
data input capture scheme and supplements the data in Table 1.
Table 5: Loopback Timing
Parameter
T_CLOCK
T_{CLKOUT_PHASE}
DQS Delay from IOB to LUT
DQS Local Clock Route Delay
Total DQS Delay
Leading edge
delays (ps)
Trailing edge
delays (ps)
6024
3012
Delay Details for DQS
450
450
397
397
847
847
Meaning
Master clock period.
Clock phase (half period).
DQS line delay from output of LUT delay element.
The LUT delay on DQS is not considered
because both DQS and rst_dqs_div signals are
by delayed the same amount.
rst_dqs_div Delay from IOB to LUT
delayed_rst_dqs_div Delay to OR
Gate
OR Gate Delay
fifo_1_wen Delay from OR Gate
Delay Details for Loopback
388
388
Constrained using MAXDELAY constraints.
Value from PAR report.
1290
1290
Constrained using MAXDELAY constraints.
Value from PAR report.
620
620
Implemented in a single LUT.
854
854
Constrained using MAXDELAY constraints.
Value from PAR report.
Total Loopback Signal Delay
Margin
3152
3719
3152
3719
Sum of all delays listed.
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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