XAPP454 Datasheet, PDF (14/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

Reference Design
Reference
Design
R
The DDR2 SDRAM controller reference design is integrated into the MIG tool. This tool has
been integrated with the Xilinx CORE Generator™ software. For the latest version of the
design, download the IP update from:
http://www.xilinx.com/support/download/index.htm.
Table 7 shows the reference design matrix.
Table 7: Reference Design Matrix
Parameter
Description
General
Developer Name
Xilinx
Target Devices (Stepping Level, ES, Production, Speed Grades)
Spartan-3A DSP FPGA
XC3SD3400A-4FG676,
Spartan-3A FPGA
XC3S700A-4FG484
Source Code Provided?
HDL code is generated by
MIG tool
Source Code Format
VHDL, Verilog
Design Uses Code or IP from Existing Reference Design,
Yes
Application Note, 3rd party, or CORE Generator Software?
Simulation
Functional Simulation Performed?
Yes
Timing Simulation Performed?
Yes
Testbench Provided for Functional and Timing Simulations?
Yes
Testbench Format
VHDL, Verilog
Simulator Software and Version
ModelSim 6.3c
SPICE/IBIS Simulations?
No
Implementation
Synthesis Software Tools and Version
XST, version 10.1
Implementation Software Tools and Version
ISE^® software, version 10.1
Static Timing Analysis Performed?
Yes
Hardware Verification
Hardware Verified?
Yes
Hardware Platform Used for Verification
Spartan-3A FPGA Starter Kit,
Spartan-3A DSP FPGA 3400A
Development Board
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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