XAPP454 Datasheet, PDF (2/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

DDR2 SDRAM Controller Modules
R
X-Ref Target - Figure 1
User Interface
Implementation Layer
Infrastructure
Datapath
Control
Physical Layer
X454_01_032008
Figure 1: Interface Layering Model
DDR2 SDRAM
Controller
Modules
X-Ref Target - Figure 2
Figure 2 is a block diagram of the DDR2 SDRAM interface for the Spartan-3 generation FPGA.
All four blocks shown in this figure are subblocks of the ddr2_top module. The function of each
block is explained in the following sections.
cmd_ack, init_done,
auto_ref_req, ar_done
Main
Top
Controller
user_input_address
user_command_register
burst_done
ddr_address_cntrl
ddr_ba_cntrl
ddr_rasb_cntrl
ddr_casb_cntrl
ddr_web_cntrl
ddr_cke_cntrl
ddr_csb_cntrl
Datapath
Data Read
user_output_data
Read Address
FIFO
dq
Read Data
FIFO
user_data_val
user_input_data
user_data_mask
dqs_delayed_col
Data Read
Controller
Data Write
dqs_int_delay_in
data_mask_f
data_mask_r
write_data_falling
write_data_rising
Controller
IOBs
Datapath
IOBs
rst_dqs_div
ddr2_ck
ddr2_ck_n
ddr2_cke
ddr2_cs_n
ddr2_ras_n
ddr2_cas_n
ddr2_we_n
ddr2_odt
ddr2_dqs
ddr2_dq
ddr2_ba
ddr2_a
DDR2
SDRAM
Infrastructure Top
Clock DCM
delay_sel_val
Calibration Top
delay_sel
Infrastructure
Infrastructure
IOBs
Figure 2: DDR2 SDRAM Interface Modules
X454_02_043008
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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