XAPP454 Datasheet, PDF (3/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

DDR2 SDRAM Controller Modules
R
Controller
The controller supports burst lengths of four and eight, and a CAS latency of three. The
controller initializes the EMR(2) and EMR(3) registers during the Load Mode command and
also generates differential data strobes.
The controller accepts user commands, decodes these user commands, and generates read,
write, and refresh commands to the DDR2 SDRAM. The controller also generates signals for
other modules.
Datapath
The datapath module is responsible for transmitting data to and receiving data from the
memories. Major functions include:
• Writing data to the memory
• Reading data from the memory
• Transferring the read data from the memory clock domain to the FPGA clock domain
The write data and strobe are clocked out of the FPGA. The strobe is center aligned with
respect to the data during writes. For DDR2 SDRAM memories, the strobe is non-free running.
To meet these requirements, the write data is clocked out using a clock that is shifted 90°
(CLK90) and 270° (CLK270) from the primary clock going to the memory. CLK270 is generated
locally from CLK90 through clock inversion. The data strobes are generated out of primary
clocks going to the memory.
Memory read data is edge aligned with a source-synchronous clock. The data is received using
the non-free running strobe and transferred to the FPGA clock domain. The input side of the
data uses resources similar to the input side of the strobe. This ensures matched delays on
data and strobe signals until the strobe is delayed in the strobe delay circuit.
Read Data Capture
During a read transaction, the DDR2 SDRAM device sends the DQS strobe and associated
data to the FPGA. DQS is edge aligned with the data. Capturing the data is a challenging task
in source-synchronous interfaces that run at high frequencies. The data changes at every edge
of DQS and the strobe is not free running. Read data from the memory device is captured
directly into the FPGA logic using a delayed DQS. The DQS delay mechanism is explained in
“Delay Circuits,” page 8.
Instead of registering the data in the input/output blocks (IOBs), a look-up table (LUT)-based
dual-port distributed RAM is used for data capture. This is a simpler method of data capture
with no need of second stage recapturing to the system clock domain. The LUT RAM is
configured as a pair of FIFOs, and each data bit is input into both FIFOs, as shown in Figure 3.
These 16-entry-deep FIFOs are asynchronous and have independent read and write ports.
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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