XAPP454 Datasheet, PDF (8/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

DDR2 SDRAM Controller Modules
R
calibration, including all the component and route delays. The calibration circuit selects the
number of delay elements for any given time. After the calibration is done, the calibration circuit
adjusts the select lines for the delay circuit.
Delay Circuits
The total strobe delay must fall within a data valid window. Therefore, the strobe is delayed
using internal delay elements. The delay elements consist of LUTs and other resources in the
FPGA fabric. Selecting the elements and routing resources used within those elements defines
the delay values precisely.
Figure 9 illustrates the manner in which LUTs are configured to create delay elements. The
nominal delay for each LUT is 620 ps in a Spartan-3A device of -5 speed grade.
X-Ref Target - Figure 9
Output
LUT
LUT
LUT
LUT
LUT
LUT
X454_09_030508
Figure 9: Building Delay Elements Using LUTs in a Xilinx FPGA
Delay Circuit Timing Analysis
All timing analysis is done using a -5 speed grade XC3S700A-5FG484 device at 166 MHz.
Table 1 illustrates the timing analysis for the FIFO-based data capture scheme described in
“Read Data Capture,” page 3. On the left and right banks, the local clock net delay is relatively
small. A single vertical Full Hex (VFULLHEX) line is used for local clock distribution. Because
of this, it is possible to easily control the overall strobe delay to fall within the calculated window.
As described in “Delay Circuits,” the overall strobe delay is controlled with the delay circuit. The
performance of designs in which the DDR2 is implemented on the left or right side of the FPGA
is 166 MHz or 333 Mb/s on a -5 speed grade device.
Table 1: Read Data Timing
Parameter
Value
(ps)
T_CLOCK
T_{CLOCK_PHASE}
T_{CLOCK_DUTY_CYCLE_DIST}
T_{DATA_PERIOD}
6024
3012
410
2602
T_DQSQ
300
Leading Edge
Uncertainties
(ps)
0
0
300
Trailing Edge
Uncertainties
(ps)
0
0
Meaning
Clock period (1/f).
Clock phase is half of T_CLOCK.
Duty cycle distortion of clock to memory.
Total data period, which is equal to
T_{CLOCK_PHASE} – T_{CLOCK_DUTY_CYCLE_DIST.}
Strobe to data distortion from Micron
MT47H16M16BG-37E DDR2 SDRAM
Data Sheet [Ref 1].
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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