XAPP454 Datasheet, PDF (10/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

DDR2 SDRAM Controller Modules
R
Table 2: LUT Selection for Left and Right Implementations (Cont’d)
Parameter (ps)
Nominal
90%
80%
Data Valid Window (Upper Bound)
1897
1923
1948
70%
1974
60%
1999
50%
2025
40%
2050
Notes:
1. In this table, the clock frequency is 166 MHz and the clock period is 6024 ps. The implementation is targeted to the XC3S700A-5FG484
device and interfaced to the Micron MT47H16M16XX-37E DDR2 SDRAM.
2. The total DQS delay in the table is generated from the MIG tool, version 2.1. DQS delay is the total delay for the route taken by the DQS from
the input pad to the delay circuit plus the total number of LUT delays and the local clock route delay. The total extra DQS delay is the total
DQS delay minus the data delay. This value should always fall within the data valid window.
3. Timing analysis is provided for the absolute minimum delay across process, temperature, and voltage variation.
X-Ref Target - Figure 10
Figure 10 shows the delay path of the DQ and DQS read capturing scheme. DQS at the FIFO
is well inside the data valid window of DQ at the FIFO.
DQS at IOB
DQ at IOB
DQ at FIFO
DVW Upperbound
DVW Lowerbound
DQ Data Delay
DQS Delay before LUT
DQS after LUT
DQS Delay IOB to LUT
Total LUT Delay
Local CLK Route Delay
DQS at FIFO
Figure 10: DQ and DQS Captured Read Timing
X454_10_040808
Table 3 shows the timing budget of the output data generation scheme when the
Spartan-3A FPGA transmits data to the memory device using DDR output flip-flops.
Table 3: Write Data Timing
Parameter
Value
(ps)
Clock Frequency (MHz)
T_CLOCK
T_{CLOCK_PHASE}
T_{CLOCK_DUTY_CYCLE_DIST}
166
6024
3012
410
T_{DATA_PERIOD}
T_{DSa (REF)}
2602
350
Leading Edge
Uncertainties
(ps)
350
Trailing Edge
Uncertainties
(ps)
Meaning
Clock frequency (f).
Clock period.
Clock phase is half of T_CLOCK.
CLKOUT_DUTY_CYCLE_DLL parameter
from Spartan-3A FPGA Family: Data
Sheet [Ref 2].
Data period is T_{CLOCK_PHASE} –
T_{CLOCK_DUTY_CYCLE_DIST.}
DQ and DM logic level input setup time
relative to DQS from
MT47H16M16BG-37E Data Sheet [Ref 1].
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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