XAPP454 Datasheet, PDF (6/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

DDR2 SDRAM Controller Modules
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X-Ref Target - Figure 6
The timing diagrams of Figure 6 show how data is captured into FIFO_0, FIFO_1, and FIFO
Write Enable.
DQS at Memory
dqs_div_rst at IOB
dqs_div_rst before LUT
rst_dqs_div after LUT
delayed_rst_dqs_div
FIFO_wr_en after OR gate
FIFO0_wr_en at FIFO
FIFO1_wr_en at FIFO
DQS before LUT
DQS after LUT
DQS at FIFO
DQ Data at FIFO
FIFO_0 Data
FIFO_1 Data
D0
D1
D2
D3
D4
D5
D6
D7
D0
D2
D4
D6
D1
D3
D5
Figure 6: Timing Diagrams of FIFO_0, FIFO_1, and FIFO Write Enable
D7
X454_06_033108
Infrastructure
The top-level Infrastructure module generates the FPGA clocks and reset signals. A Digital
Clock Manager (DCM) is used to generate CLK0 and CLK90. A delay calibration circuit is also
implemented in this module.
Delay Calibration Circuit
Several factors can affect the centering of DQS in the DQ data valid window. Due to process,
voltage, and temperature variations, the LUT delay can vary from 250 ps to 625 ps in the
Spartan-3 family. The process variation is calibrated by the delay calibration circuit to select the
correct number of taps in the DQS tap delay circuit at reset and power-up. As temperature or
voltage drift up or down, the delay calibration circuit continuously calibrates to position the DQS
in the center of the DQ data valid window.
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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