XAPP454 Datasheet, PDF (4/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

DDR2 SDRAM Controller Modules
R
X-Ref Target - Figure 3
FIFO_0
Delayed DQS
FIFO_0_wr_en
Data
FIFO_1
Data to User
Delayed DQS #
FIFO_1_wr_en
Figure 3: FIFO Block Diagram
X454_03_031908
Read Data Clocking
Read data from the memory is written into FIFO_0 on the rising edge of the delayed DQS, and
into FIFO_1 on the falling edge of the delayed DQS. Data can be read out of both FIFO_0 and
FIFO_1 simultaneously.
The FIFO write pointer is clocked using the delayed DQS. FIFO read pointers are clocked in the
FPGA internal clock domain. The FIFOs are written when the FIFO write enable signal is
asserted. Generation of the FIFO write enable signal is explained in detail in “Write Enable
Generation,” page 5.
The FIFO write enable signal is generated from a signal named rst_dqs_div, which is asserted
at any time during the preamble for the DQS. This signal is deasserted at any time during the
last two DQS phases. Figure 4 illustrates the idea behind rst_dqs_div.
X-Ref Target - Figure 4
Logic to
Generate
rst_dqs_div
Last Register
in IOB
Delay
Normalization
Loop
LUT Delay
Circuit
Write Enable
Generation
Logic
Write
Pointers
Read Data
FIFO
Figure 4: Circuit Illustrating rst_dqs_div Signal
X454_04_032708
The rst_dqs_div signal is driven to an IOB as an output and is then taken as an input through
the input buffer. This technique normalizes the IOB and trace delays between rst_dqs_div and
the DQS clock signals. The rst_dqs_div from the input pad of the FPGA uses identical routing
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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