XAPP454 Datasheet, PDF (5/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

DDR2 SDRAM Controller Modules
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resources as the DQS before it enters the LUT delay circuit. The trace delay of the loop should
be the sum of the trace delays of the clock forwarded to the memory and the DQS.
The LUT delay circuit shown in Figure 4 is identical to the LUT delay circuit used for the delayed
DQS. This ensures that rst_dqs_div and the delayed DQS signals take identical paths and have
similar delays before being sent to the FIFO write pointers and FIFO write enable inputs.
Write Enable Generation
Figure 5 shows the circuit for write enable generation. The FIFO_0 write enable signal is the
logical OR of rst_dqs_div and the registered version of the rst_dqs_div output. FIFO_1 is
enabled after the first positive transition of the delayed DQS signal. This logic eliminates false
latching of data into the FIFOs. It also eliminates false incrementing of the write pointers during
the preamble period of the delayed DQS 3-state-to-Low transition and the postamble period of
the delayed DQS High-to-3-state transition.
X-Ref Target - Figure 5
Input
IOB
rqs_div_rst
LUT Delay
Circuit
rst_dqs_div
FIFO_1_wen
FIFO_0_wen
DQS at FIFO
Figure 5: FIFO Write Enable Generation
X454_05_043008
The registered output enables the FIFOs and FIFO write pointers during the postamble period
when rst_dqs_div is deasserted. The registered rst_dqs_div flag is cleared on the last trailing
edge of the delayed DQS, and the FIFOs and FIFO write pointers are disabled.
Figure 6 shows the timing diagram for dqs_div_rst, rst_dqs_div, and the FIFO write enable
signals. The total delay of rst_dqs_div and the FIFO write enable signals should not exceed one
memory clock cycle. The Memory Interface Generator (MIG) tool generates the necessary
constraints for dqs_div_rst, rst_dqs_div, and the FIFO write enable signals in the user
constraints file (UCF) with the MAXDELAY constraint to ensure that the write enable signals
meet the setup time.
Data is latched into the FIFOs when the delayed DQS toggles. The FIFO_0 and FIFO_1 write
pointers are enabled when rst_dqs_div is asserted. Data is latched into FIFO_0 on the rising
edge of the delayed DQS, and the FIFO_0 write pointer increments on the same edge. Data is
latched into FIFO_1 on the falling edge of the delayed DQS, and the FIFO_1 write pointer
increments on the same edge.
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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