XAPP454 Datasheet, PDF (1/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

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XAPP454 (v2.1) January 20, 2009
Application Note: Spartan-3 Generation FPGAs
DDR2 SDRAM Interface for
Spartan-3 Generation FPGAs
Author: Samson Ng
Summary
This application note describes a DDR2 SDRAM interface implementation in a
Spartan^®-3 generation FPGA, interfacing with a Micron DDR2 SDRAM device. This document
provides a brief overview of the DDR2 SDRAM device features, followed by a detailed
explanation of the DDR2 SDRAM interface implementation.
DDR2 SDRAM
Device
Overview
The DDR2 SDRAM interface is source-synchronous, supporting double-data rate transfers like
DDR SDRAM, and uses the SSTL 1.8V I/O standard, providing significant system power
savings. DDR2 SDRAM is only available in FBGA packages. These packages have greatly
reduced parasitics as compared to TSOP packages for DDR SDRAM. The DDR2 SDRAM bus
is clocked at twice the speed of DDR SDRAM and uses 4n prefetch instead of 2n prefetch.
DDR2 SDRAM devices achieve high-speed operation by transferring data on both the rising
and falling edges of the clock signal. The memory operates using a differential clock provided
by the controller. Commands are registered at every positive edge of the clock. A bidirectional
data strobe (DQS) is transmitted along with the data for use in data capture at the receiver.
During reads, DQS is transmitted by the DDR2 SDRAM device and is edge aligned with data.
During writes, DQS is transmitted by the controller and is center aligned with data.
Read and write accesses to the DDR2 SDRAM device are burst oriented. Accesses begin with
the registration of an active command and are then followed by a read or write command. The
address bits registered coincident with the active command are used to select the bank and
row to be accessed. The address bits registered with the read or write command are used to
select the bank and starting column location for the burst access.
Interface Model
The DDR2 SDRAM interface is layered to simplify the design and make it modular. Figure 1
shows the layered memory interface. The three layers consist of an application layer, an
implementation layer, and a physical layer.
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XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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