XAPP454 Datasheet, PDF (11/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

DDR2 SDRAM Controller Modules
R
Table 3: Write Data Timing (Cont’d)
Parameter
Value
(ps)
T_{DHa (REF)}
350
T_{PACKAGE_SKEW}
T_{CLOCK_TREE_SKEW}
T_{CLKOUT_PHASE}
60
50
210
T_JITTER
0
T_{PCB_LAYOUT_SKEW}
50
Total Uncertainties
Margin
1162
Leading Edge
Uncertainties
(ps)
0
60
50
210
0
50
720
Trailing Edge
Uncertainties
(ps)
350
60
50
210
0
50
720
Meaning
DQ and DM logic level hold time relative to
DQS from MT47H16M16BG-37E
Data Sheet.
Package skew.
Clock tree skew.
Phase offset between DCM outputs from
Spartan-3A FPGA Family: Data
Sheet [Ref 2].
The FPGA and DDR2 devices have a
common clock. Thus, the effective jitter is
zero.
Skew between data and strobes on the
board.
• Leading edge uncertainties is the
sum of T_DS, T_{PACKAGE_SKEW},
T_{CLOCK_TREE_SKEW},
T_{CLKOUT_PHASE}, T_JITTER, and
T_{PCB_LAYOUT_SKEW.}
• Trailing edge uncertainties is the sum
of T_DH, T_{PACKAGE_SKEW},
T_{CLOCK_TREE_SKEW},
T_{CLKOUT_PHASE}, T_JITTER, and
T_{PCB_LAYOUT_SKEW.}
Margin is equal to T_{DATA_PERIOD} –
(Leading edge uncertainties + Trailing
edge uncertainties).
Table 4 shows the timing budget of the output address and control generation scheme when
the Spartan-3A FPGA accesses the memory device using single data rate (SDR) output
flip-flops.
Table 4: Address and Command Data Timing
Parameter
Clock frequency (MHz)
T_CLOCK
T_IS
Value (ps)
166
6024
500
Leading edge
uncertainties
500
Trailing edge
uncertainties
0
Meaning
Clock frequency (f).
Clock period (1/f).
Address and control input setup time from
MT47H16M16BG-37E Data Sheet [Ref 1].
T_IH
500
0
500
Address and control input hold time from
MT47H16M16BG-37E Data Sheet.
T_{PACKAGE_SKEW}
T_JITTER
60
60
0
0
T_{CLOCK_TREE_SKEW}
50
50
60
Package skew.
0
The FPGA and DDR2 devices have a
common clock. Thus, the effective jitter is
zero.
50
Clock tree skew.
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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