XAPP454 Datasheet, PDF (13/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

User Interface Signals
R
Table 6 shows the timing budget and evaluates the path from the system clock source, through
the Spartan-3A FPGA, to the clock input on the memory device.
Table 6: Clock-to-Memory Timing
Parameter
Leading edge
delays (ps)
Trailing edge
delays (ps)
Meaning
T_CLOCK
T_{CLKOUT_PHASE}
CLKIN_CYC_JITT_DLL_HF
6024
3012
150
Master clock period.
Clock phase (half period).
150
Cycle-to-cycle jitter of the oscillator. Maximum
value is set to CLKIN_CYC_JITT_DLL_HF from
Spartan-3A FPGA data sheet [Ref 2].
CLKOUT_DUTY_CYCLE_DLL
250
250
DCM and BUFG duty cycle distortion from
CLKOUT_DUTY_CYCLE_DLL parameter (1% of
CLKIN period [T_CLOCK] plus 190 ps) for CLK0
and CLK90.
Clock Phase from DCM and BUFG
Memory Clock Jitter
2687
125
3337
125
Derived after duty cycle distortion and half of the
jitter values are subtracted from T_{CLKOUT_PHASE}.
Taken from MT47H16M16BG-37E Data
Sheet [Ref 1].
Memory Duty Cycle Distortion
2711
3313
Taken from MT47H16M16BG-37E Data Sheet.
Memory Input Clock Timing
2643
3396
Derived after jitter and duty cycle distortion
parameters are applied to the input clock.
Margin
44
59
Local Clocking Resources
The delayed strobe in this design uses the local clocking resources available in the device for
the clock routing. Full hex lines (spanning six configurable logic blocks) that have low skew are
located throughout the device.
The left and right implementations use VFULLHEX lines for local clock routing. The top and
bottom implementations use vertical long (VLONG), VFULLHEX, and horizontal Full Hex
(HFULLHEX) lines for local clock routing. This route is more complex than the left and right
sides. The delay and skew of this local clock route is higher than the left and right local clock
routes. This results in a limit of 133 MHz memory clock speed in a top and bottom
implementation.
IOBS
All FPGA input and output signals are implemented in the IOBS module. All address and
control signals are registered going into and coming out of the IOBS module.
User Interface
Signals
For a detailed description of the user interface signals and a write/read diagram, refer to the
Xilinx Memory Interface Generator (MIG) User Guide [Ref 3].
DDR2 SDRAM
Auto Refresh
The DDR2 SDRAM must be refreshed once every 7.8 μs with an auto_refresh command. The
auto_refresh command is asserted with SYS_CLK. The ar_done signal is asserted by the
DDR2 SDRAM controller upon completion of the auto_refresh command.
XAPP454 (v2.1) January 20, 2009
www.xilinx.com
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