XAPP454 Datasheet, PDF (7/15 Pages) Xilinx, Inc – DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

DDR2 SDRAM Controller Modules
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The LUT delays in the delay circuit are measured using the tap delay circuit shown in Figure 7.
Each inverter in the tap delay circuit is created using a LUT. Similarly, each multiplexer in
Figure 9 is built using a LUT. This calibration circuit does not require additional DCMs or global
buffers (BUFGs).
X-Ref Target - Figure 7
CLK
TAP0
TAP1
TAP2
TAP31
Figure 7: Tap Delay Circuit Built Using LUTs
Figure 8 shows the waveforms generated by the tap delay circuit.
X-Ref Target - Figure 8
X454_07_031108
CLK
TAP31
TAP5
TAP4
TAP3
TAP2
TAP1
TAP0
0 1111
0 0 00 0
1111 0
00 011
1100 0
0 1111
Figure 8: Tap Delay Waveforms
X454_08_030508
Each of the tap delays in Figure 8 has its input inverted. The nominal LUT delay in the
XC3S700A-5FG484 device is 620 ps. For a 166 MHz design, there are five or six LUTs in a
clock phase. The edge pattern (10101101011010 or 0101001010010) is generated from the
tap circuit. The patterns are registered at the rising clock boundary through a chain of flip-flops.
The tap delay circuit creates two rising edges that are then counted by a phase counter using
the same clock to count how many taps are in a clock phase. The calibrated tap values are then
used to determine how many MUXs are needed to position the DQS strobe line.
The number of taps required for a clock phase is determined by the specific FPGA used. If a
faster FPGA is chosen, the number of LUT delays in the strobe path is increased by the delay
calibration logic to ensure that the strobe is still within the valid data window. If the
Spartan-3 generation FPGA becomes faster due to process variations or any other reason, the
number of tap delays for the same clock phase is automatically increased by the delay
calibration logic.
The delay calibration circuit selects the number of delay elements used to delay the strobe lines
with respect to the read data. The delay calibration circuit calculates the delay of a circuit that
is identical in all respects to the strobe delay circuit. All aspects of the delay are considered for
XAPP454 (v2.1) January 20, 2009
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