W28V400B Datasheet, PDF (8/48 Pages) Winbond – 4M(512K x 8/256K x 16) SMARTVOLTAGE FLASH MEMORY

W28V400B/T
7. PRINCIPLES OF OPERATION
The W28V400B/T SmartVoltage Flash memory includes an on-chip WSM to manage block erase and
word/byte write functions. It allows for 100 percent TTL-level control inputs, fixed power supplies
during block erase, full chip erase, word/byte write and lock-bit configuration, and minimal processor
overhead with RAM-like interface timings.
After initial device power-up or return from reset mode (see Bus Operations section), the device
defaults to read array mode. Manipulation of external memory control pins allow array read, standby
and output disable operations.
Status register and identifier codes can be accessed through the CUI independent of the V_PP voltage.
High voltage on V_PP enables successful block erase, word/byte writing. All functions associated with
altering memory contents (block erase, word/byte write, status and identifier codes) are accessed via
the CUI and verified through the status register.
Commands are written using standard microprocessor write timings. The CUI contents serve as input
to the WSM, which controls the block erase and word/byte write. The internal algorithms are regulated
by the WSM, including pulse repetition, internal verification and margining of data. Addresses and
data are internally latched during write cycles. Writing the appropriate command outputs array data,
accesses the identifier codes, or outputs status register data.
Interface software that initiates and polls progress of block erase and word/byte write can be stored in
any block. This code is copied to and executed from system RAM during flash memory updates. After
successful completion, reads are again possible via the Read Array command. Block erase suspend
allows system software to suspend a block erase to read/write data from/to blocks other than that
which is suspend. Word/byte write suspend allows system software to suspend a word/byte write to
read data from any other flash memory array location.
Data Protection
Depending on the application, the system designer may choose to make the V_PP power supply
switchable (available only when memory block erases or word/byte writes are required) or hardwired
to V_PPH1/2/3. The device accommodates either design practice and encourages optimization of the
processor-memory interface.
When V_PP ≤ V_PPLK, memory contents cannot be altered. The CUI, with two-step block erase or
word/byte write command sequences, provides protection from unwanted operations even when high
voltage is applied to V_PP. All write functions are disabled when V_DD is below the write lockout voltage
V_LKO or when #RESET is at V_IL. The device’s boot blocks locking capability for #WP provides
additional protection from inadvertent code or data alteration by block erase and word/byte write
operations.
Refer to Table 6 for write protection alternatives.
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