W28V400B Datasheet, PDF (22/48 Pages) Winbond – 4M(512K x 8/256K x 16) SMARTVOLTAGE FLASH MEMORY

W28V400B/T
10. DESIGN CONSIDERATIONS
Three-line Output Control
This device will often be used in large memory arrays. Winbond provides three control inputs to
accommodate multiple memory connections. Three-line control provides for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not occur.
To use these control inputs efficiently, an address decoder should enable #CE while #OE should be
connected to all memory devices and the system’s #READ control line. This assures that only
selected memory devices have active outputs while deselected memory devices are in standby mode.
#RESET should be connected to the system POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD should also toggle during system reset.
RY/#BY, Block Erase and Word/Byte Write Polling
RY/#BY is a full CMOS output that provides a hardware method of detecting block erase and
word/byte write completion. It transitions low after block erase or word/byte write commands and
returns to V_OH when the WSM has finished executing the internal algorithm.
RY/#BY can be connected to an interrupt input of the system CPU or controller. It is active at all times.
RY/#BY is also V_OH when the device is in block erase suspend (with word/byte write inactive),
word/byte write suspend or deep power-down modes.
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers
are interested in three supply current issues; standby current levels, active current levels and transient
peaks produced by falling and rising edges of #CE and #OE. Transient current magnitudes depend on
the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 µF ceramic capacitor connected between V_DD and V_SS and between
V_PP and V_SS. These high frequency, low inductance capacitors should be placed as close as possible
to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed
at the array’s power supply connection between V_DD and V_SS. The bulk capacitor will overcome
voltage drops caused by PC board trace inductance.
V_PP Trace on Printed Circuit Boards
Updating flash memories that reside in the target system requires that the printed circuit board
designer pay attention to the V_PP power supply trace. The V_PP pin supplies the memory cell current for
word/byte writing and block erasing. Use similar trace widths and layout considerations given to the
V_DD power bus. Adequate V_PP supply traces and decoupling will decrease V_PP voltage spikes and
overshoots.
V_DD, VPP, #RESET Transitions
Block erase and word/byte write are not guaranteed if V_PP falls outside of a valid VPPH1/2/3 range, V_DD
falls outside of a valid V_DD1/2/3/4 range, or #RESET ≠ V_IH or V_HH. If V_PP error is detected, status register
bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If #RESET
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