W28V400B Datasheet, PDF (41/48 Pages) Winbond – 4M(512K x 8/256K x 16) SMARTVOLTAGE FLASH MEMORY

W28V400B/T
Reset Operations
RY/#BY(R)
V _OH
V _OL
V _IH
#RESET(P)
V _IL
V _OH
RY/#BY(R)
V _OL
#RESET(P) ^VIH
V _IL
t _PLPH
(A)Reset During Read Array Mode
t _PLRH
t _PLPH
(B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration
2.7V/3.3V/5V
V_DD
VIL
V _IH
#RESET(P)
V _IL
t _235VPH
(C)#RESET Rising Timing
Reset AC Specifications
Figure 17. AC Waveform for Reset Operation
SYM.
PARAMETER
V_DD = 2.7V − 3.6V V_DD = 3.0V − 3.6V V_DD = 4.5V − 5.5V _UNIT
Min. Max. Min. Max. Min. Max.
#RESET Pulse Low Time
t_PLPH (If RP# is tied to VDD, this specification
100
100
100
nS
is not applicable)
t_PLRH
#RESET Low to Reset during Block
Erase or Word/Byte Write (Note 1, 2)
22
20
12
µS
V_DD 2.7V to #RESET High
t_235VPH VDD 3.0V to #RESET High
100
100
100
nS
V_DD 4.5V to #RESET High (Note 3)
Notes:
1. If #RESET is asserted while a block erase or word/byte write operation is not executing, the reset will complete within 100nS.
2. A reset time, t_PHQV, is required from the later of RY/#BY or #RESET going high until outputs are valid.
3. When the device power-up, holding #RESET low minimum 100 nS is required after V_DD has been in predefined range and
also has been in stable there.
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Publication Release Date: April 11, 2003
Revision A4