W28V400B Datasheet, PDF (5/48 Pages) Winbond – 4M(512K x 8/256K x 16) SMARTVOLTAGE FLASH MEMORY

W28V400B/T
The access time is 85ns (t_AVQV) over the commercial temperature range (0° C to +70° C) and V_DD
supply voltage range of 4.75V to 5.25V. At lower V_DD voltages, the access times are 90ns (4.5V to
5.5V), 100 nS (3.0V to 3.6V) and 120 nS (2.7V to 3.6V).
The Automatic Power Savings (APS) feature substantially reduces active current when the device is in
static mode (addresses not switching). In APS mode, the typical I_CCR current is 1mA at V_DD = 5V.
When #CE and #RESET pins are at V_DD, the I_CC CMOS standby mode is enabled. When the #RESET
pin is at V_SS, deep power-down mode is enabled which minimizes power consumption and provides
write protection during reset. A reset time (tPHQV) is required from #RESET switching high until
outputs are valid. Likewise, the device has a wake time (tPHEL) from #RESET-high until writes to the
CUI are recognized. With #RESET at V_SS, the WSM is reset and the status register is cleared.
The device is available in 48-lead TSOP (Thin Small Outline Package, 1.2 mm thick). Pinout is shown
in Figure 2.
4. BLOCK DIAGRAM
Output Buffer
Output
Multiplexer
A0-A17
Input
Buffer
Y
Decoder
Address
Latch
X
Decoder
Address
Counter
DQ0 -DQ15
Input Buffer
Identifier
Register
Status
Register
Data
Comparator
Data
Register
Y-Gating
32K-Word
(64K-Byte)
Main Blocks
x7
I/O Logic
Command
User
Interface
A-1
VDD
#BYTE
#CE
#WE
#OE
#RESET
#WP
Write
State
Machine
Program/Erase
Voltage Switch
RY/#BY
VPP
VDD
VSS
Figure 1. Block Diagram
Publication Release Date: April 11, 2003
-5-
Revision A4