W29GL256SH9T-TR Datasheet, PDF (71/88 Pages) Winbond – 256M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE

W29GL256S
10.2.2 Hardware Reset
Hardware Reset is initiated by the #RESET signal going to VIL. The device will draw ICC7 current
during Hardware Reset (tRPH). The device draws CMOS standby current (ICC4), if #RESET is
constantly held at VSS, but if #RESET is held at VIL and not VSS, the standby current is higher.
If #RESET is asserted LOW after tVCS and Power-up Reset has not completed, in this case the
Power-up #RESET Internal Algorithms will be performed instead and not Hardware #RESET,
requiring a period of tVCS to complete.
After the device has completed Power Up Reset and entered the Standby mode, any transition to the
Hardware Reset mode will initiate the Hardware Reset Internal Algorithm. A Hardware Reset is
considerably shorter than a Power-up Reset (tRPH) to complete. During the Hardware Reset Internal
Algorithms, any Internal Algorithm in progress will be terminated and the Write State Controller is
returned to its Power Up Reset mode without reloading Write State Controller algorithms from non-
volatile memory. When the Hardware Reset Internal Algorithms finishes, the device will remain in the
Hardware Reset mode, if #RESET stays LOW. If #RESET returns HIGH, the device will go into the
Standby mode. If #RESET is HIGH at the end of the Hardware Reset Internal Algorithms, the device
will go into the Standby mode.
If the Power Up Reset cycle was not properly finished by the end of tVCS period, a transition to the
Hardware Reset mode will only cause a transition to the Power Up Reset mode and initiate the
Power-up Reset Internal Algorithm. This makes sure the device can complete a Power-up Reset
sequence even if some portion of the Power Up voltage ramp-up causes the Power Up Reset to not
initiate or finish properly. During Power-up or Hardware reset, the RY/#BY pin is LOW as an
indicating the device is busy.
Figure 10-4 Hardware Reset
Publication Release Date: Jul 02, 2014
Revision C
71