W29GL256SH9T-TR Datasheet, PDF (55/88 Pages) Winbond – 256M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE

W29GL256S
Legend:
X = Don't care.
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector selected. Address bits A23-A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same Line.
WC = Word Count is the number of write buffer locations to load minus 1.
Notes:
1. See Interface Condition Table for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle during Read, ID/CFI Read (Manufacturing ID /
Device ID), Indicator Bits, Security Sector Region Read, SSR Lock Read, and 2nd cycle of Status Register Read.
4. Data bits DQ15-DQ8 are don't care in command sequences, except for RD, PD, WC and PWD.
5. Address bits A23-A11 is don't care for unlock and command cycles, unless SA or PA required. (A23 is the Highest
Address pin.).
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the CFI-ID (Autoselect) mode, or
if DQ5 goes HIGH (while the device is providing status data).
8. Command is valid when device is ready to read array data or when device is in CFI-ID (Autoselect) mode.
9. The system can read and program/program suspend in non-erasing sectors, or enter the CFI-ID MMO, when in the
Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
10. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes.
11. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state.
IMPORTANT: the full command sequence is required if resetting out of ABORT.
12. The Exit command returns the device to reading the array.
13. All Lock Register bits are one-time programmable. The program state = 0 and the erase state = 1. Also, the
Individual Protection mode Lock Bit cannot be programmed at the same time or the Lock Register Bits Program
operation aborts and returns the device to read mode. Lock Register bits that are reserved for future uses are
undefined and may be 0’s or 1's.
14. If any of the Entry commands was issued, an Exit command must be issued to reset the device into read mode.
Publication Release Date: Jul 02, 2014
Revision C
55