W29GL256SH9T-TR Datasheet, PDF (12/88 Pages) Winbond – 256M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE

W29GL256S
6 INTRODUCTION
The W29GL256S is a 3V, 256-Mbit, non-volatile, flash memory device with variable I/O. The device
has a bus width of 16-bits (2-Bytes/1-Word) and word address boundaries are what are used. All read
accesses provide 16 bits of data on every bus cycle. Every write cycle transfers 16 bits of data on the
bus.
XIP and Data Storage flash memories are combined features of the W29GL256S. This enables the
ability of fast programming speeds and reduced random access time of XIP flash in higher densities.
Read access to any random location takes 90 ns to 100 ns depending on device I/O power supply
voltage. Each random access reads an aligned group of data of 32-bytes called a Page. Other words
within the same Page may be read by changing only the low order 4 bits of word address. While in
the same Page, access could take between 15 ns to 30 ns. This read operation is referred as Page
Mode. Higher word address bits will select a different Page and begin another initial access. All read
accesses are asynchronous.
The device control logic is divided into two parallel operating subsections, the Command State
Machine (CSM) and the Write State Controller. Device level signals with the host system during read
and write transfers are monitored by the CSM as needed for the inputs and drive outputs. CSM
delivers data from the current entered address map on read operations; places write address and
data information into the Write State Controller command memory; signals the Write State Controller
of power level changes, write operations and hardware reset, The Write State Controller looks in the
command memory, after a write operation, for correct command sequences and performs Internal
Algorithms that are related.
Within the W29GL256S lie internal complex sequential operations or algorithms that are necessary to
change the state of non-volatile data in the memory array. The internal Write State Controller
manages all device algorithms. The main array data, programming and erasure are the main
algorithms that are performed. When the host system sends command instructions to the flash device
address space and Write State Controller receives these commands, provides status information
during the progress of internal algorithms and performs all the necessary steps to complete the
command.
A logical 1 bit is considered an erased cell. Changing a bit from a logical 1 to a logical 0 is considering
programming. Note, only an erase operation is able to change a 0 to a 1. A restriction to an erase
operation is a minimum of an entire sector (sector erase), which is a 128-kbyte aligned and length
group of data is erased or the entire array can be erased (chip erase). Winbond ships the
W29GL256S with all sectors erased.
Publication Release Date: Jul 02, 2014
Revision C
12