W29GL256SH9T-TR Datasheet, PDF (69/88 Pages) Winbond – 256M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE

W29GL256S
10.2 Power Up Reset and Hardware Reset
Decoupling the VCC and EVIO power supplies are normal precautions that should be taken.
Generally, a suitable capacitor would be on the order of 0.1 μF tied close to the package.
Table 10-2 Power ON and Reset Parameters
Description
VCC Setup Time to first access^1,2
EVIO Setup Time to first access^1,2
#RESET LOW to #CE LOW
#RESET Pulse Width
Time between #RESET (HIGH) and #CE (LOW)
#CE Pulse Width HIGH
Parameter
tVCS
tVIOS
tRPH
tRP
tRH
tCEH
Limit
Min
Min
Min
Min
Min
Min
Value
300
300
35
200
50
20
Unit
μs
μs
μs
ns
ns
ns
Notes:
1. Not 100% tested.
2. Timing measured from VCC minimum and EVIO minimum to VIH on Reset and VIL on #CE.
3. #RESET low is possible during Power Up Reset. If RESET is asserted during Power Up Reset, the later period of
tRPH, tVIOS, or tVCS will determine when #CE may go LOW. If #RESET stays LOW after tVIOS, or tVCS is fulfilled, tRPH
is measured from the end of tVIOS, or tVCS. RESET is required also to be HIGH tRH before #CE goes LOW.
4. During power-up, VCC ≥ (EVIO - 200 mV).
5. The ramp rate for VCC and EVIO can be non-linear.
6. tRPH must be  (tRP + tRH).
10.2.1 Power Up Reset
The device will draw ICC7 current during Power-up Reset.
As power supplies voltage ramps up, the EVIO voltage must remain less than or equal to the VCC
voltage. VIH also has to be less than or equal to the EVIO voltage.
The Power-up Reset Internal Algorithm requires a period of tVCS to load all of the Write State
Controller algorithms and default data from non-volatile memory. All control signals including #CE and
#RESET during the Power-up Reset period are ignored. Higher than normal Power Up Reset current
during tVCS may occur if #CE is LOW, but the level of #CE will not influence the Power-up Reset
Internal Algorithms. For a valid read or write operation, #CE or #OE must transition from HIGH to
LOW after the tVCS period. During the period of tVCS, #RESET can be HIGH or LOW. When #RESET
is LOW during the period of tVCS, it may stay LOW at the end of tVCS to keep the device in the
Hardware Reset mode. The device will go to the Standby mode if #RESET is HIGH at the end of tVCS.
Publication Release Date: Jul 02, 2014
Revision C
69