W29GL256SH9T-TR Datasheet, PDF (49/88 Pages) Winbond – 256M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE

W29GL256S
8.17 Inherent Data Protection
8.17.1 Command Protection
Internal Algorithms are started by writing command sequences into the Write State Controller
command memory. The command memory array is not readable from the bus interface and has no
memory map overlay. Each bus interface write is a command or a segment of a command sequence
to the device. The Write State Controller analyses the address and data in each write transfer to
decide whether the write is part of a legitimate command sequence. When a correct command
sequence is finished the Write State Controller will start the appropriate Internal Algorithm.
Writing an incorrect command sequence, can most likely result in the Write State Controller returning
to its Standby mode. However, there is a possibility that an improper command sequence may cause
the device to go into an unknown state, in that case a reset command must be executed or possibly a
hardware reset, to return the Write State Controller to its Standby mode.
Publication Release Date: Jul 02, 2014
Revision C
49