W29GL256SH9T-TR Datasheet, PDF (50/88 Pages) Winbond – 256M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE

W29GL256S
8.18 Operating Modes and Signal States Table
Mode
Table 8-7 Interface Conditions
Signal
VCC
EVIO
#CE
#OE
#WE
#RESET
A[23:0]
DQ[15:0]
≥ VCC min
≥ EVIO min ≤
VCC
VIL
VIL
VIH
VIH
A[23:4]
Valid
A[3:0]
Modified
Valid Output
≥ VCC
min
≥ EVIO
min
VIL
VIL
VIH
VIH
Valid
Valid
Output
≥ VCC
min
≥ EVIO
min ≤
VCC
VIL
VIH
VIH
VIH
Valid
HI-Z
≥ VCC
min
≥ EVIO
min ≤
VCC
VIL
VIH
VIL
VIH
≥ VCC min
≥ EVIO min ≤
VCC
VIL
X
X
VIH
≥ VCC
min
≥ EVIO
min ≤
VCC
VIH
X
X
VIH
Valid
Valid
X
Valid
Input
Available
Output
HI-Z
≥ VCC
min
≥ EVIO
min ≤
VCC
X
X
X
VIL
X
HI-Z
This table describes the required condition of each interface signal for each operating mode.
≥ VCC
min
≥ EVIO
min ≤
VCC
X
X
X
X
X
HI-Z
Legend:
X = Don’t Care
Valid = all bus signals have stable L or H level
Modified = valid state different from a previous valid state
Available = read data is internally stored with output driver controlled by #OE
Notes:
1. #WE and #OE cannot be at VIL at the same time.
2. Read with Output Disable is a read initiated with #OE HIGH.
3. Automatic Sleep is a read/write operation where data has been driven on the bus for an extended period, without
#CE going HIGH and the device internal logic has gone into standby mode to conserve power.
Publication Release Date: Jul 02, 2014
Revision C
50