W948D6FBHX5E-TR Datasheet, PDF (53/60 Pages) Winbond – 256Mb Mobile LPDDR

W948D6FB / W948D2FB
256Mb Mobile LPDDR
Notes:
1. All voltages referenced to VSS.
2. All parameters assume proper device initialization.
3. Tests for AC timing may be conducted at nominal supply voltage levels, but the related specifications and
device operation are guaranteed for the full voltage and temperature range specified.
4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters
of the part. It is not intended to be either a precise representation of the typical system environment nor a
depiction of the actual load presented by a production tester. System designers will use IBIS or other
simulation tools to correlate the timing reference load to system environment. Manufacturers will correlate to
their production test conditions (generally a coaxial transmission line terminated at the tester electronics). For
the half strength driver with a nominal 10pF load parameters tAC and tQH are expected to be in the same
range. However, these parameters are not subject to production test but are estimated by design /
characterization. Use of IBIS or other simulation tools for system design validation is suggested.
I/O
Time Reference Load
Z₀ = 50 Ohms
20pF
5. The CK/ CK input reference voltage level (for timing referenced to CK/ CK ) is the point at which CK and CK
cross; the input reference voltage level for signals other than CK/ CK is VDDQ/2.
6. The timing reference voltage level is VDDQ/2.
7. AC and DC input and output voltage levels are defined in the section for Electrical Characteristics and AC/DC
operating conditions.
8. A CK/ CK differential slew rate of 2.0 V/ns is assumed for all parameters.
9. CAS latency definition: with CL = 3 the first data element is valid at (2 * tCK + tAC) after the clock at which
the READ command was registered; with CL = 2 the first data element is valid at (tCK + tAC) after the clock at
which the READ command was registered
10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to
the device (i.e. this value can be greater than the minimum specification limits of tCL and tCH)
11. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or
clock low (tCL, tCH). tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the
worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition,
both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel
variation of the output drivers.
12. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh
modes.
13. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input
signals, and VIH(DC) to VIL(AC) for falling input signals.
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold
times. Signal transitions through the DC region must be monotonic.
15. Input slew rate ≥ 1.0 V/ns.
16. Input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
17. These parameters guarantee device timing but they are not necessarily tested on each device.
18. The transition time for address and command inputs is measured between VIH and VIL.
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Publication Release Date : Oct, 15, 2012
Revision : A01-004