W948D6FBHX5E-TR Datasheet, PDF (45/60 Pages) Winbond – 256Mb Mobile LPDDR

W948D6FB / W948D2FB
256Mb Mobile LPDDR
7.14 Clock Stop
Stopping a clock during idle periods is an effective method of reducing power consumption.
The LPDDR SDRAM supports clock stop under the following conditions:
 the last command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has
executed to completion, including any data-out during read bursts; the number of clock pulses per access
command depends on the device‟s AC timing parameters and the clock frequency;
 the related timing conditions (tRCD, tWR, tRP, tRFC, tMRD) has been met;
 CKE is held High
When all conditions have been met, the device is either in “idle state” or “row active state” and clock stop mode
may be entered with CK held Low and CK held High.
Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next
access command may be applied. Additional clock pulses might be required depending on the system
characteristics.
The following Figure shows clock stop mode entry and exit.
 Initially the device is in clock stop mode
 The clock is restarted with the rising edge of T0 and a NOP on the command inputs
 With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for
clock stop as soon as this access command is completed
 Tn is the last clock pulse required by the access command latched with T1
 The clock can be stopped after Tn
7.14.1 Clock Stop Mode Entry and Exit
T0
CK
CK
T1
T2
Tn
CKE
Timing
Condition
Command
NOP
CMD
NOP
NOP
NOP
Address
DQ,DQS
Valid
(High-Z)
Clock
Stopped
Exit Clock
Stop
Mode
Valid
Command
= Don't Care
Enter Clock
Stop Mode
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Publication Release Date : Oct, 15, 2012
Revision : A01-004